I can speak to the signal path portion. When your sample rate exceeds 61.44 MSPS, the video trigger moves from the API to the FPGA. It triggers on the amplitude of the raw 250 MSPS data, before the digital bandpass filter is applied. There is significant rolloff beyond the 160 MHz point, but triggering can still occur. The thought was if you are video triggering on a signal contained within the 160 MHz bandwidth, it would be transparent to the user, but energy just outside the 160 MHz bandwidth is the exception.
This was resolved in the SM200C, since we filter and resample more aggressively on the FPGA and trigger on the PC, but I realize this doesn’t help you.
Hysteresis: I would love to hear more about what you had in mind, and if you can give us a use case. More advanced triggering is something we have talked about and would like to explore. Obviously there are a lot more options at the API level than the FPGA level.
